On the structural analysis of CMOS and bipolar analog integrated circuits

The design of analog integrated circuits is a complicated process that is still mostly done by hand. To speed up this process, automatie design tools have been designed to assist the designers. Especially automatic sizing, i. e., automatie assignment of values to circuit elements, e. g., transistor geometries, in order to optimise a circuit's performance has been weil developed during the past decades. However, a mathematical optimiser can drive the circuit into technically meaningless regions. A circuit might perform weil in the nominal case, but fail under disadvantageous operating conditions. Experimental results show that the performance and robustness of a design can be improved if additional constraints - so-calied sizing rules - are considered. Sizing rules arise already on transistor level, e. g., a CMOS transistor usually must not leave the saturation region. These sizing rules occur in the form of equalities and inequalities between electrical or geometrical parameters. Besides, they can be c1assified into sizing rules that ensure the correct function of a circuit and sizing rule that lead to higher robustness. In this work, a profound hierarchie library of elementary circuit building blocks in both CMOS and Bipolar technology is presented. The Iibrary contains basic twotransistor blocks like the simple current mirror or the differential pair, but also larger blocks like bigger current mirrors or the differential stage. For each single block, a set of generic sizing rules has been defined. Consequently, all sizing rules applying for a whole circuit can be determined by collecting the sizing rules for all the basic building blocks it consists of.