Cryptography and cryptanalysis on reconfigurable devices

For many cryptographic applications, dedicated hardware circuits provide the optimal ratio with respect of costs and performance. This thesis presents novel hardware implementations of cryptographic and cryptanalytic algorithms for reconfigurable devices. In the first part of this work, the author proposes distinct high-performance implementations for symmetric and asymmetric cryptosystems on modern Field Programmable Gate Arrays (FPGA) and graphics cards. For these devices, new design strategies for the symmetric AES blockcipher as well as asymmetric RSA and ECC cryptosystems are presented. The second part of this thesis focuses on cluster architectures for cryptanalysis based on reconfigurable devices. This comprises implementations for attacks on the symmetric DES block cipher as well as on asymmetric security assumptions such as the elliptic curve discrete logarithm and the factorization problem. The last contribution considers the protection of reconfigurable systems themselves and their internal security-related components. Most FPGAs are volatile devices that allow logical reconfiguration using configuration bit files. This thesis covers strategies to efficiently protect Intellectual Property (IP) contained in such configurations bit files. A final aspect of this part also discusses solutions for the installation of trustworthy security functions on FPGAs.