Resilient cross-layer design of digital integrated circuits

In the past, manufacturing technology alone had to ensure resilience of integrated circuits. This assumption is no longer tenable in future nanometer technologies. The task of ensuring system resilience has to be distributed over all hierarchy levels – from technology up to system level. After introducing compact models for technology-level faults, this thesis presents several methods for analyzing circuit resilience. These methods enable the consideration of use-profile variations, workload, and instruction impact. Finally, the resilience of an embedded system considering different actuators is evaluated using a statistical fault-injection framework.